#include "ddrc_init.h"
/*************************************LP4 DMC PHY DTMG**********************************************/
/*-------------------1866--------------------*/
#define	DMC_PHY_LP4_1866_DTMG0		0x1800001E    			/*0x40,CFG0_TMG*/
#define	DMC_PHY_LP4_1866_DTMG1		0x00007FFC			/*0x44,CFG1_TMG*/
#if LP4X_ODT_EN(7)
#define DMC_PHY_LP4_1866_DTMG2		0x000003FE			/*0x48,CFG2_TMG*/
#else
#define DMC_PHY_LP4_1866_DTMG2		0x000001f8
#endif
#define	DMC_PHY_LP4_1866_DTMG3		0x00007FFC			/*0x4C,CFG3_TMG*/
#define	DMC_PHY_LP4_1866_DTMG4		0x0000003C			/*0x50,CFG4_TMG*/
//According ODT Status Choose DQS gate Timming Select
/*LPDDR4X*/
#if LP4X_ODT_EN(7)
#define	DMC_PHY_LP4_1866_DTMG5_LP4X	0x80400060  		 //Timming	/*0x54,CFG5_TMG*/
#else
#define	DMC_PHY_LP4_1866_DTMG5_LP4X	0x80400060
#endif
/*LPDDR4*/
#if LP4_ODT_EN(7)
#define	DMC_PHY_LP4_1866_DTMG5_LP4	0x80400060
#else
#define	DMC_PHY_LP4_1866_DTMG5_LP4	0x80400060
#endif
#define	DMC_PHY_LP4_1866_DTMG6		0x01100100			/*0x58,CFG6_TMG*/
#define	DMC_PHY_LP4_1866_DTMG7		0x000Afffe			/*0x5C,CFG7_TMG*/
#define	DMC_PHY_LP4_1866_DTMG8		0x860890fc			/*0x60,CFG8_TMG*/
#define	DMC_PHY_LP4_1866_DTMG9		0x80000030			/*0x64,CFG_DLL_AC0_DL_0*/
#define	DMC_PHY_LP4_1866_DTMG10		0x80000030			/*0x68,CFG_DLL_AC1_DL_0*/
#define	DMC_PHY_LP4_1866_DTMG11		0x8000808c			/*0x6C,CFG_DLL_DS0_DL_0*/
#define	DMC_PHY_LP4_1866_DTMG12		0x80000010			/*0x70,CFG_DLL_DS0_DL_1*/
#define	DMC_PHY_LP4_1866_DTMG13		0x80000010			/*0x74,CFG_DLL_DS0_DL_2*/
#define	DMC_PHY_LP4_1866_DTMG14		0x20000000			/*0x78,CFG_DLL_DS0_DL_3*/
#define	DMC_PHY_LP4_1866_DTMG15		0x0				/*0x7C,CFG_DLL_DS0_DL_4*/

#define	DMC_PHY_LP4_1866_DTMG19		0x8000808c			/*0x8C,CFG_DLL_DS1_DL_0*/
#define	DMC_PHY_LP4_1866_DTMG20		0x80000010			/*0x90,CFG_DLL_DS1_DL_1*/
#define	DMC_PHY_LP4_1866_DTMG21		0x80000010			/*0x94,CFG_DLL_DS1_DL_2*/
#define	DMC_PHY_LP4_1866_DTMG22		0x00000000			/*0x98,CFG_DLL_DS1_DL_3*/
#define	DMC_PHY_LP4_1866_DTMG23		0x0				/*0x9C,CFG_DLL_DS1_DL_4*/
#define	DMC_PHY_LP4_1866_DTMG27		0x8000808c			/*0xAC,CFG_DLL_DS2_DL_0*/
#define	DMC_PHY_LP4_1866_DTMG28		0x80000010			/*0xB0,CFG_DLL_DS2_DL_1*/
#define	DMC_PHY_LP4_1866_DTMG29		0x80000010			/*0xB4,CFG_DLL_DS2_DL_2*/
#define	DMC_PHY_LP4_1866_DTMG30		0x00000000			/*0xB8,CFG_DLL_DS2_DL_3*/
#define	DMC_PHY_LP4_1866_DTMG31		0x0				/*0xBC,CFG_DLL_DS2_DL_4*/

#define	DMC_PHY_LP4_1866_DTMG35		0x8000808c			/*0xCC,CFG_DLL_DS3_DL_0*/
#define	DMC_PHY_LP4_1866_DTMG36		0x80000010			/*0xD0,CFG_DLL_DS3_DL_1*/
#define	DMC_PHY_LP4_1866_DTMG37		0x80000010			/*0xD4,CFG_DLL_DS3_DL_2*/
#define	DMC_PHY_LP4_1866_DTMG38		0x00000000			/*0xD8,CFG_DLL_DS3_DL_3*/
#define	DMC_PHY_LP4_1866_DTMG39		0x0				/*0xDC,CFG_DLL_DS3_DL_4*/

#define	DMC_PHY_LP4_1866_DTMG43		0x00157040			/*0xEC,CFG_DSKPLL_CFG0*/
#define	DMC_PHY_LP4_1866_DTMG44		0x0043F000			/*0xF0,CFG_DSKPLL_CFG1*/

//According ODT Status and DDR Type Choose DQS gate Timming Select
/*LPDDR4X*/
/******************************
DTMG45 :io ds odt vrefi
bit[31:24]:rf_phy_io_vrefi_adj

bit[22]:rf_phy_io_ds_dq_ib4
bit[21]:rf_phy_io_ds_dq_ibc
*******************************/

#if LP4X_ODT_EN(7)
#define	DMC_PHY_LP4_1866_DTMG45_LP4X	0x50700066	/*0xF4,CFG_IO_DS_CFG*/
#else
#define	DMC_PHY_LP4_1866_DTMG45_LP4X	0x23465066
#endif
/*LPDDR4*/
#if LP4_ODT_EN(7)
#define	DMC_PHY_LP4_1866_DTMG45_LP4	0x0A465066
#else
#define	DMC_PHY_LP4_1866_DTMG45_LP4	0x0A465066
#endif

/*-------------------1536--------------------*/
#define DMC_PHY_LP4_1536_DTMG0		0x1800001e
#define DMC_PHY_LP4_1536_DTMG1		0x00001ffc
#if LP4X_ODT_EN(6)
#define DMC_PHY_LP4_1536_DTMG2		0x000003FE
#else
#define DMC_PHY_LP4_1536_DTMG2		0x000001f8
#endif
#define DMC_PHY_LP4_1536_DTMG3		0x00001ffc
#define DMC_PHY_LP4_1536_DTMG4		0x0000003c
/*LPDDR4X*/
#if LP4X_ODT_EN(6)
#define DMC_PHY_LP4_1536_DTMG5_LP4X	0x80400060
#else
#define DMC_PHY_LP4_1536_DTMG5_LP4X	0x80400060
#endif
/*LPDDR4*/
#if LP4_ODT_EN(6)
#define DMC_PHY_LP4_1536_DTMG5_LP4	0x80400060
#else
#define DMC_PHY_LP4_1536_DTMG5_LP4	0x80400060
#endif
#define DMC_PHY_LP4_1536_DTMG6		0x01100040
#define DMC_PHY_LP4_1536_DTMG7		0x000A3ffe
#define DMC_PHY_LP4_1536_DTMG8		0x860890fc
#define DMC_PHY_LP4_1536_DTMG9		0x80000030
#define DMC_PHY_LP4_1536_DTMG10		0x80000030
#define DMC_PHY_LP4_1536_DTMG11		0x80008075
#define DMC_PHY_LP4_1536_DTMG12		0x80000010
#define DMC_PHY_LP4_1536_DTMG13		0x80000010
#define DMC_PHY_LP4_1536_DTMG14		0x20000000
#define DMC_PHY_LP4_1536_DTMG15		0x0

#define DMC_PHY_LP4_1536_DTMG19		0x80008075
#define DMC_PHY_LP4_1536_DTMG20		0x80000010
#define DMC_PHY_LP4_1536_DTMG21		0x80000010
#define DMC_PHY_LP4_1536_DTMG22		0x0
#define DMC_PHY_LP4_1536_DTMG23		0x0
#define DMC_PHY_LP4_1536_DTMG24		0x0
#define DMC_PHY_LP4_1536_DTMG25		0x0
#define DMC_PHY_LP4_1536_DTMG26		0x0
#define DMC_PHY_LP4_1536_DTMG27		0x80008075
#define DMC_PHY_LP4_1536_DTMG28		0x80000010
#define DMC_PHY_LP4_1536_DTMG29		0x80000010
#define DMC_PHY_LP4_1536_DTMG30		0x0
#define DMC_PHY_LP4_1536_DTMG31		0x0

#define DMC_PHY_LP4_1536_DTMG35		0x80008075
#define DMC_PHY_LP4_1536_DTMG36		0x80000010
#define DMC_PHY_LP4_1536_DTMG37		0x80000010
#define DMC_PHY_LP4_1536_DTMG38		0x0
#define DMC_PHY_LP4_1536_DTMG39		0x0

#define DMC_PHY_LP4_1536_DTMG43		0x00157040
#define DMC_PHY_LP4_1536_DTMG44		0x00435000

//According ODT Status and DDR Type Choose DQS gate Timming Select
/*LPDDR4X*/
#if LP4X_ODT_EN(6)
#define DMC_PHY_LP4_1536_DTMG45_LP4X	0x50700066
#else
#define DMC_PHY_LP4_1536_DTMG45_LP4X	0x23465066
#endif
/*LPDDR4*/
#if LP4_ODT_EN(6)
#define DMC_PHY_LP4_1536_DTMG45_LP4	0x0A465066
#else
#define DMC_PHY_LP4_1536_DTMG45_LP4	0x0A465066
#endif

/*-------------------1333--------------------*/
#define DMC_PHY_LP4_1333_DTMG0		0x1800001E
#define DMC_PHY_LP4_1333_DTMG1		0x00000FFC
#if LP4X_ODT_EN(5)
#define DMC_PHY_LP4_1333_DTMG2		0x000003FE
#else
#define DMC_PHY_LP4_1333_DTMG2		0x000001f8
#endif

#define DMC_PHY_LP4_1333_DTMG3		0x00000FFc
#define DMC_PHY_LP4_1333_DTMG4		0x0000003C

#if LP4X_ODT_EN(5)
#define DMC_PHY_LP4_1333_DTMG5_LP4X	0x80400030
#else
#define DMC_PHY_LP4_1333_DTMG5_LP4X	0x80400030
#endif
/*LPDDR4*/
#if LP4_ODT_EN(5)
#define DMC_PHY_LP4_1333_DTMG5_LP4	0x80400030
#else
#define DMC_PHY_LP4_1333_DTMG5_LP4	0x80400030
#endif
#define DMC_PHY_LP4_1333_DTMG6		0x01100040
#define DMC_PHY_LP4_1333_DTMG7		0x000a1ffe
#define DMC_PHY_LP4_1333_DTMG8		0x860890fc
#define DMC_PHY_LP4_1333_DTMG9		0x80000030
#define DMC_PHY_LP4_1333_DTMG10		0x80000030
#define DMC_PHY_LP4_1333_DTMG11		0x8000806c
#define DMC_PHY_LP4_1333_DTMG12		0x80000010
#define DMC_PHY_LP4_1333_DTMG13		0x80000010
#define DMC_PHY_LP4_1333_DTMG14		0x20000000
#define DMC_PHY_LP4_1333_DTMG15		0x00000000

#define DMC_PHY_LP4_1333_DTMG19		0x8000806c
#define DMC_PHY_LP4_1333_DTMG20		0x80000010
#define DMC_PHY_LP4_1333_DTMG21		0x80000010
#define DMC_PHY_LP4_1333_DTMG22		0x00000000
#define DMC_PHY_LP4_1333_DTMG23		0x00000000
#define DMC_PHY_LP4_1333_DTMG24		0x00000000
#define DMC_PHY_LP4_1333_DTMG25		0x00000000
#define DMC_PHY_LP4_1333_DTMG26		0x00000000
#define DMC_PHY_LP4_1333_DTMG27		0x8000806c
#define DMC_PHY_LP4_1333_DTMG28		0x80000010
#define DMC_PHY_LP4_1333_DTMG29		0x80000010
#define DMC_PHY_LP4_1333_DTMG30		0x00000000
#define DMC_PHY_LP4_1333_DTMG31		0x00000000

#define DMC_PHY_LP4_1333_DTMG35		0x8000806c
#define DMC_PHY_LP4_1333_DTMG36		0x80000010
#define DMC_PHY_LP4_1333_DTMG37		0x80000010
#define DMC_PHY_LP4_1333_DTMG38		0x00000000
#define DMC_PHY_LP4_1333_DTMG39		0x00000000

#define DMC_PHY_LP4_1333_DTMG43		0x00157040
#define DMC_PHY_LP4_1333_DTMG44		0x0042A000
//According ODT Status and DDR Type Choose DQS gate Timming Select
/*LPDDR4X*/
#if LP4X_ODT_EN(5)
#define DMC_PHY_LP4_1333_DTMG45_LP4X	0x50700066
#else
#define DMC_PHY_LP4_1333_DTMG45_LP4X	0x23465066
#endif
/*LPDDR4*/
#if LP4_ODT_EN(5)
#define DMC_PHY_LP4_1333_DTMG45_LP4	0x0A465066
#else
#define DMC_PHY_LP4_1333_DTMG45_LP4	0x0A465066
#endif



/*-------------------1024--------------------*/
#define DMC_PHY_LP4_1024_DTMG0		0x1800001E
#define DMC_PHY_LP4_1024_DTMG1		0x000007FC
#if LP4X_ODT_EN(4)
#define DMC_PHY_LP4_1024_DTMG2		0x000003FE
#else
#define DMC_PHY_LP4_1024_DTMG2		0x000001f8
#endif
#define DMC_PHY_LP4_1024_DTMG3		0x000007FF
#define DMC_PHY_LP4_1024_DTMG4		0x0000003C
/*LPDDR4X*/
#if LP4X_ODT_EN(4)
#define DMC_PHY_LP4_1024_DTMG5_LP4X	0x80400030
#else
#define DMC_PHY_LP4_1024_DTMG5_LP4X	0x80400030
#endif
/*LPDDR4*/
#if LP4_ODT_EN(4)
#define DMC_PHY_LP4_1024_DTMG5_LP4	0x80400030
#else
#define DMC_PHY_LP4_1024_DTMG5_LP4	0x80400030
#endif

#define DMC_PHY_LP4_1024_DTMG6		0x01100040
#define DMC_PHY_LP4_1024_DTMG7		0x000a0ffe
#define DMC_PHY_LP4_1024_DTMG8		0x880890fC
#define DMC_PHY_LP4_1024_DTMG9		0x80000030
#define DMC_PHY_LP4_1024_DTMG10		0x80000030
#define DMC_PHY_LP4_1024_DTMG11		0x80008054
#define DMC_PHY_LP4_1024_DTMG12		0x80000020
#define DMC_PHY_LP4_1024_DTMG13		0x80000020
#define DMC_PHY_LP4_1024_DTMG14		0x20000000
#define DMC_PHY_LP4_1024_DTMG15		0x00000000

#define DMC_PHY_LP4_1024_DTMG19		0x80008054
#define DMC_PHY_LP4_1024_DTMG20		0x80000020
#define DMC_PHY_LP4_1024_DTMG21		0x80000020
#define DMC_PHY_LP4_1024_DTMG22		0x00000000
#define DMC_PHY_LP4_1024_DTMG23		0x00000000
#define DMC_PHY_LP4_1024_DTMG24		0x00000000
#define DMC_PHY_LP4_1024_DTMG25		0x00000000
#define DMC_PHY_LP4_1024_DTMG26		0x00000000
#define DMC_PHY_LP4_1024_DTMG27		0x80008054
#define DMC_PHY_LP4_1024_DTMG28		0x80000020
#define DMC_PHY_LP4_1024_DTMG29		0x80000020
#define DMC_PHY_LP4_1024_DTMG30		0x00000000
#define DMC_PHY_LP4_1024_DTMG31		0x00000000

#define DMC_PHY_LP4_1024_DTMG35		0x80008054
#define DMC_PHY_LP4_1024_DTMG36		0x80000020
#define DMC_PHY_LP4_1024_DTMG37		0x80000020
#define DMC_PHY_LP4_1024_DTMG38		0x00000000
#define DMC_PHY_LP4_1024_DTMG39		0x00000000

#define DMC_PHY_LP4_1024_DTMG43		0x00157040
#define DMC_PHY_LP4_1024_DTMG44		0x00423000

//According ODT Status and DDR Type Choose DQS gate Timming Select
/*LPDDR4X*/
#if LP4X_ODT_EN(4)
#define DMC_PHY_LP4_1024_DTMG45_LP4X	0x50700066
#else
#define DMC_PHY_LP4_1024_DTMG45_LP4X	0x23465066
#endif
/*LPDDR4*/
#if LP4_ODT_EN(4)
#define DMC_PHY_LP4_1024_DTMG45_LP4	0x0A465066
#else
#define DMC_PHY_LP4_1024_DTMG45_LP4	0x0A465066
#endif


/*-------------------768--------------------*/
#define DMC_PHY_LP4_768_DTMG0		0x1800001E
#define DMC_PHY_LP4_768_DTMG1		0x000001FC
#define DMC_PHY_LP4_768_DTMG2		0x000001F8
#define DMC_PHY_LP4_768_DTMG3		0x000001FF
#define DMC_PHY_LP4_768_DTMG4		0x0000003C
#if LP4X_ODT_EN(3)
#define DMC_PHY_LP4_768_DTMG5_LP4X	0x004000F8
#else
#define DMC_PHY_LP4_768_DTMG5_LP4X	0x004000F8
#endif
/*LPDDR4*/
#if LP4_ODT_EN(3)
#define DMC_PHY_LP4_768_DTMG5_LP4	0x004000F8
#else
#define DMC_PHY_LP4_768_DTMG5_LP4	0x004000F8
#endif
#define DMC_PHY_LP4_768_DTMG6		0x01100020
#define DMC_PHY_LP4_768_DTMG7		0x0
#define DMC_PHY_LP4_768_DTMG8		0x0A0890f4
#define DMC_PHY_LP4_768_DTMG9		0x80000030
#define DMC_PHY_LP4_768_DTMG10		0x80000030
#define DMC_PHY_LP4_768_DTMG11		0x80008044
#define DMC_PHY_LP4_768_DTMG12		0x80000020
#define DMC_PHY_LP4_768_DTMG13		0x80000020
#define DMC_PHY_LP4_768_DTMG14		0x20000000
#define DMC_PHY_LP4_768_DTMG15		0x00000000

#define DMC_PHY_LP4_768_DTMG19		0x80008044
#define DMC_PHY_LP4_768_DTMG20		0x80000020
#define DMC_PHY_LP4_768_DTMG21		0x80000020
#define DMC_PHY_LP4_768_DTMG22		0x00000000
#define DMC_PHY_LP4_768_DTMG23		0x00000000
#define DMC_PHY_LP4_768_DTMG24		0x00000000
#define DMC_PHY_LP4_768_DTMG25		0x00000000
#define DMC_PHY_LP4_768_DTMG26		0x00000000
#define DMC_PHY_LP4_768_DTMG27		0x80008044
#define DMC_PHY_LP4_768_DTMG28		0x80000020
#define DMC_PHY_LP4_768_DTMG29		0x80000020
#define DMC_PHY_LP4_768_DTMG30		0x00000000
#define DMC_PHY_LP4_768_DTMG31		0x00000000

#define DMC_PHY_LP4_768_DTMG35		0x80008044
#define DMC_PHY_LP4_768_DTMG36		0x80000020
#define DMC_PHY_LP4_768_DTMG37		0x80000020
#define DMC_PHY_LP4_768_DTMG38		0x00000000
#define DMC_PHY_LP4_768_DTMG39		0x00000000

#define DMC_PHY_LP4_768_DTMG43		0x00107140
#define DMC_PHY_LP4_768_DTMG44		0x00419000

//According ODT Status and DDR Type Choose DQS gate Timming Select
/*LPDDR4X*/
#if LP4X_ODT_EN(3)
#define DMC_PHY_LP4_768_DTMG45_LP4X	0x50700066
#else
#define DMC_PHY_LP4_768_DTMG45_LP4X	0x50700066
#endif
/*LPDDR4*/
#if LP4_ODT_EN(3)
#define DMC_PHY_LP4_768_DTMG45_LP4	0x22700066
#else
#define DMC_PHY_LP4_768_DTMG45_LP4	0x22700066
#endif


/*-------------------512--------------------*/
#define DMC_PHY_LP4_512_DTMG0		0x3800001E
#define DMC_PHY_LP4_512_DTMG1		0x000000FC
#define DMC_PHY_LP4_512_DTMG2		0x000001F8
#define DMC_PHY_LP4_512_DTMG3		0x000000FF
#define DMC_PHY_LP4_512_DTMG4		0x0000003C
#define DMC_PHY_LP4_512_DTMG5		0x00400078
#define DMC_PHY_LP4_512_DTMG6		0x01100010
#define DMC_PHY_LP4_512_DTMG7		0x00000000
#define DMC_PHY_LP4_512_DTMG8		0x000890f4
#define DMC_PHY_LP4_512_DTMG9		0x80008000
#define DMC_PHY_LP4_512_DTMG10		0x80008000
#define DMC_PHY_LP4_512_DTMG11		0x80008040
#define DMC_PHY_LP4_512_DTMG12		0x80000020
#define DMC_PHY_LP4_512_DTMG13		0x80000020
#define DMC_PHY_LP4_512_DTMG14		0x20000000
#define DMC_PHY_LP4_512_DTMG15		0x00000000

#define DMC_PHY_LP4_512_DTMG19		0x80008040
#define DMC_PHY_LP4_512_DTMG20		0x80000020
#define DMC_PHY_LP4_512_DTMG21		0x80000020
#define DMC_PHY_LP4_512_DTMG22		0x00000000
#define DMC_PHY_LP4_512_DTMG23		0x00000000
#define DMC_PHY_LP4_512_DTMG24		0x00000000
#define DMC_PHY_LP4_512_DTMG25		0x00000000
#define DMC_PHY_LP4_512_DTMG26		0x00000000
#define DMC_PHY_LP4_512_DTMG27		0x80008040
#define DMC_PHY_LP4_512_DTMG28		0x80000020
#define DMC_PHY_LP4_512_DTMG29		0x80000020
#define DMC_PHY_LP4_512_DTMG30		0x00000000
#define DMC_PHY_LP4_512_DTMG31		0x00000000

#define DMC_PHY_LP4_512_DTMG35		0x80008040
#define DMC_PHY_LP4_512_DTMG36		0x80000020
#define DMC_PHY_LP4_512_DTMG37		0x80000020
#define DMC_PHY_LP4_512_DTMG38		0x00000000
#define DMC_PHY_LP4_512_DTMG39		0x00000000

#define DMC_PHY_LP4_512_DTMG43		0x00107140
#define DMC_PHY_LP4_512_DTMG44		0x00411000
#define DMC_PHY_LP4_512_DTMG45		0x50700066

/*-------------------384--------------------*/
#define DMC_PHY_LP4_384_DTMG0		0x3800001E
#define DMC_PHY_LP4_384_DTMG1		0x0000007c
#define DMC_PHY_LP4_384_DTMG2		0x000001F8
#define DMC_PHY_LP4_384_DTMG3		0x0000007F
#define DMC_PHY_LP4_384_DTMG4		0x0000003C
#define DMC_PHY_LP4_384_DTMG5		0x0040003c
#define DMC_PHY_LP4_384_DTMG6		0x01100008
#define DMC_PHY_LP4_384_DTMG7		0x00000000
#define DMC_PHY_LP4_384_DTMG8		0x160890fD
#define DMC_PHY_LP4_384_DTMG9		0x80008000
#define DMC_PHY_LP4_384_DTMG10		0x80008000
#define DMC_PHY_LP4_384_DTMG11		0x80008081
#define DMC_PHY_LP4_384_DTMG12		0x80000040
#define DMC_PHY_LP4_384_DTMG13		0x80000040
#define DMC_PHY_LP4_384_DTMG14		0x20000000
#define DMC_PHY_LP4_384_DTMG15		0x00000000

#define DMC_PHY_LP4_384_DTMG19		0x80008081
#define DMC_PHY_LP4_384_DTMG20		0x80000040
#define DMC_PHY_LP4_384_DTMG21		0x80000040
#define DMC_PHY_LP4_384_DTMG22		0x00000000
#define DMC_PHY_LP4_384_DTMG23		0x00000000
#define DMC_PHY_LP4_384_DTMG24		0x00000000
#define DMC_PHY_LP4_384_DTMG25		0x00000000
#define DMC_PHY_LP4_384_DTMG26		0x00000000
#define DMC_PHY_LP4_384_DTMG27		0x80008081
#define DMC_PHY_LP4_384_DTMG28		0x80000040
#define DMC_PHY_LP4_384_DTMG29		0x80000040
#define DMC_PHY_LP4_384_DTMG30		0x00000000
#define DMC_PHY_LP4_384_DTMG31		0x00000000

#define DMC_PHY_LP4_384_DTMG35		0x80008081
#define DMC_PHY_LP4_384_DTMG36		0x80000040
#define DMC_PHY_LP4_384_DTMG37		0x80000040
#define DMC_PHY_LP4_384_DTMG38		0x00000000
#define DMC_PHY_LP4_384_DTMG39		0x00000000

#define DMC_PHY_LP4_384_DTMG43		0x00107140
#define DMC_PHY_LP4_384_DTMG44		0x0040D000
#define DMC_PHY_LP4_384_DTMG45		0x50700066
/*-------------------256--------------------*/
#if 1//L5PRO
#define DMC_PHY_LP4_256_DTMG0		0x3800001E
#define DMC_PHY_LP4_256_DTMG1		0x0000007C
#define DMC_PHY_LP4_256_DTMG2		0x000001F8
#define DMC_PHY_LP4_256_DTMG3		0x0000007F
#define DMC_PHY_LP4_256_DTMG4		0x0000003C
#define DMC_PHY_LP4_256_DTMG5		0x0040003C
#define DMC_PHY_LP4_256_DTMG6		0x01100008
#define DMC_PHY_LP4_256_DTMG7		0x0
#define DMC_PHY_LP4_256_DTMG8		0x200890fD
#define DMC_PHY_LP4_256_DTMG9		0x80008000
#define DMC_PHY_LP4_256_DTMG10		0x80008000
#define DMC_PHY_LP4_256_DTMG11		0x8000806c
#define DMC_PHY_LP4_256_DTMG12		0x80000040
#define DMC_PHY_LP4_256_DTMG13		0x80000040
#define DMC_PHY_LP4_256_DTMG14		0x20000000
#define DMC_PHY_LP4_256_DTMG15		0x00000000
#define DMC_PHY_LP4_256_DTMG16		0x00000000
#define DMC_PHY_LP4_256_DTMG17		0x00000000
#define DMC_PHY_LP4_256_DTMG18		0x00000000
#define DMC_PHY_LP4_256_DTMG19		0x8000806c
#define DMC_PHY_LP4_256_DTMG20		0x80000040
#define DMC_PHY_LP4_256_DTMG21		0x80000040
#define DMC_PHY_LP4_256_DTMG22		0x00000000
#define DMC_PHY_LP4_256_DTMG23		0x00000000
#define DMC_PHY_LP4_256_DTMG24		0x00000000
#define DMC_PHY_LP4_256_DTMG25		0x00000000
#define DMC_PHY_LP4_256_DTMG26		0x00000000
#define DMC_PHY_LP4_256_DTMG27		0x8000806c
#define DMC_PHY_LP4_256_DTMG28		0x80000040
#define DMC_PHY_LP4_256_DTMG29		0x80000040
#define DMC_PHY_LP4_256_DTMG30		0x00000000
#define DMC_PHY_LP4_256_DTMG31		0x00000000

#define DMC_PHY_LP4_256_DTMG35		0x8000806c
#define DMC_PHY_LP4_256_DTMG36		0x80000040
#define DMC_PHY_LP4_256_DTMG37		0x80000040
#define DMC_PHY_LP4_256_DTMG38		0x00000000
#define DMC_PHY_LP4_256_DTMG39		0x00000000

#define DMC_PHY_LP4_256_DTMG43		0x00107140
#define DMC_PHY_LP4_256_DTMG44		0x00409000
#define DMC_PHY_LP4_256_DTMG45		0x50700066
#else//l5
#define	DMC_PHY_LP4_256_DTMG0		0x2800001E
#define	DMC_PHY_LP4_256_DTMG1		0x0000007C
#define	DMC_PHY_LP4_256_DTMG2		0x000001F8
#define	DMC_PHY_LP4_256_DTMG3		0x0000007F
#define	DMC_PHY_LP4_256_DTMG4		0x0000003C
#define	DMC_PHY_LP4_256_DTMG5		0x00400078
#define	DMC_PHY_LP4_256_DTMG6		0x00000008
#define	DMC_PHY_LP4_256_DTMG7		0x0000001c
#define	DMC_PHY_LP4_256_DTMG8		0x300886FF
#define	DMC_PHY_LP4_256_DTMG9		0x00000080
#define	DMC_PHY_LP4_256_DTMG10		0x00000080
#define	DMC_PHY_LP4_256_DTMG11		0x800000AF
#define	DMC_PHY_LP4_256_DTMG12		0x80000022
#define	DMC_PHY_LP4_256_DTMG13		0x80000022
#define	DMC_PHY_LP4_256_DTMG14		0x00000000
#define	DMC_PHY_LP4_256_DTMG15		0x00000000
#define	DMC_PHY_LP4_256_DTMG16		0x00000000
#define	DMC_PHY_LP4_256_DTMG17		0x00000000
#define	DMC_PHY_LP4_256_DTMG18		0x00000000
#define	DMC_PHY_LP4_256_DTMG19		0x800000AF
#define	DMC_PHY_LP4_256_DTMG20		0x80000022
#define	DMC_PHY_LP4_256_DTMG21		0x80000022
#define	DMC_PHY_LP4_256_DTMG22		0x00000000
#define	DMC_PHY_LP4_256_DTMG23		0x00000000
#define	DMC_PHY_LP4_256_DTMG24		0x00000000
#define	DMC_PHY_LP4_256_DTMG25		0x00000000
#define	DMC_PHY_LP4_256_DTMG26		0x00000000
#define	DMC_PHY_LP4_256_DTMG27		0x800000AF
#define	DMC_PHY_LP4_256_DTMG28		0x80000022
#define	DMC_PHY_LP4_256_DTMG29		0x80000022
#define	DMC_PHY_LP4_256_DTMG30		0x00000000
#define	DMC_PHY_LP4_256_DTMG31		0x00000000
#define	DMC_PHY_LP4_256_DTMG32		0x00000000
#define	DMC_PHY_LP4_256_DTMG33		0x00000000
#define	DMC_PHY_LP4_256_DTMG34		0x00000000
#define	DMC_PHY_LP4_256_DTMG35		0x800000AF
#define	DMC_PHY_LP4_256_DTMG36		0x80000022
#define	DMC_PHY_LP4_256_DTMG37		0x80000022
#define	DMC_PHY_LP4_256_DTMG38		0x00000000
#define	DMC_PHY_LP4_256_DTMG39		0x00000000
#define	DMC_PHY_LP4_256_DTMG40		0x00000000
#define	DMC_PHY_LP4_256_DTMG41		0x00000000
#define	DMC_PHY_LP4_256_DTMG42		0x00000000
#define	DMC_PHY_LP4_256_DTMG43		0x00103140
#define	DMC_PHY_LP4_256_DTMG44		0x00409000
#define	DMC_PHY_LP4_256_DTMG45		0x40700066

#endif

